资源列表
upf.v1.0
- Unified Power Format Standard
VHDL
- VHDL和数字电路设计课程实验指导，内容丰富-VHDL and digital circuit design course experiment guide, rich in content
SpW_codec_perfect
- SpaceWire 编解码器完整验证，vhdl源程序，-SpaceWire compile a complete verification of decoder, VHDL source code,
DDS_8b_zy_02
- 该程序实现FPGA实现DDS功能，配合单片机控制可实现正弦波输出。以及配合外围电路改变DA参考电压，可实现输出电压可调。-FPGA implementation of the program to achieve DDS functions, control can be achieved with sine wave output of the microcontroller. Changes in the external circuit with the DA and the refere
WCE
- up down countr with 7 segment display for spartan boards withreset and enable
Tutorial.tar
- zedboard partial reconfiguration tutorial
3_first_event_detector
- 本代码实现智力抢答器的功能，采用VHDL语言。全部实现过程全在文件里面，结构清晰，思想明了。-This code realization of intelligence responder function, using VHDL language. The whole implementation process full in files, clear structure, clear thinking.
Four-adder-of-subtracter
- 在max+plus II 的环境下设计4位全加器数字电路 使用vhdl语言，进行设计数字电路的RTL级电路 -Four full adder digital circuit design environment, max+ plus II RTL-level circuit, digital circuit design using vhdl language
SIM1
- double precision floating point algorithm implemented only division method
batch-26.rar
- IMPLEMENTATION OF SOME VHDL AND VERILOG PROGRAM IN FPGA.,IMPLEMENTATION OF SOME VHDL AND VERILOG PROGRAM IN FPGA.
uart_io_test
- verilog中UART的PC通信协议,看过的人都说好，已经验证正确性，很不错的代码。-verilog in the PC UART communication protocols, seen people say well, has verified the accuracy, very good code.
Experiment02
- 闪耀灯和流水灯,闪耀频率是指一个LED开和关的周期时间。实验二中的flash_module所制定的输出如 上。-Sparkling lights and water lights, LED flashing frequency is an on and off cycle time. Experiment II enacted in flash_module output above.