资源列表
monit
- SPI Master SPI Master SPI Master-SPI MasterSPI MasterSPI MasterSPI MasterSPI Master
1234
- adjustable watch using nexix fpga
traffic
- 本作品为一交通控制器，分为A、B两个方向。保证本作品完好，并附有仿真文件。-This works as a traffic controller , into A, B two directions . Assurance that the work intact, together with simulation files.
tanchishe
- 用硬件描述语言VHDL编写的小游戏，可下载到实验板上实现在8*8的点阵上的贪吃蛇游戏-Written using a hardware descr iption language VHDL game can be downloaded to the experimental board to achieve the 8* 8 dot matrix, Snake game
Mouse_HLD3
- 基于fpga和xinlinx ise的鼠标应用vhdl程序，希望对你有所帮助！-and they simply based on the mouse xinlinx ideally VHDL application procedures, and I hope to help you!
uart1
- 串口程序，基于VHDL 的，很好的程序 快下吧
Exemple_2_VGA
- my vhdl code to intrface with a vga my vhdl code to intrface with a vga my vhdl code to intrface with a vga my vhdl code to intrface with a vga my vhdl code to intrface with a vga-my vhdl code to intrface with a vga my vhdl code to intrface with a vg
chuankoushoufa
- 串口收发数码管显示，含vhdl，顶层文件，工程文件，经过开发板测试-Serial transceiver digital display, with vhdl, top-level files, project files, through the development board test
stopwatch.rar
- 秒表可计时，用VHDL编译的源代码，从0.1到60秒计时，解压后直接用Quartus打开project即可,Stopwatch timer can be used to compile the VHDL source code, from 0.1 to 60 seconds from time, after extracting the direct use of Quartus can open the project
verilog--divide-programs
- verilog任意分频程序，包括奇数倍分频和偶数倍分频，占空比为50 ，QuartusII上验证程序有效-verilog every divide programs, including an odd multiple divider and even multiple frequency, duty cycle 50 , the QuartusII on the verification process
AvalonInterfaceSpecification
- Avalon Bus interface specification
ramlib_06
- 这是一个有关FIFO的VHDL 程序。。。请大家下载分享。