资源列表
display_1
- veilog程序可以在fpga上完成数字钟程序(Verilog program can be completed on the digital clock fpga procedures)
VHDLReferenceManual
- ＶＨＤＬ语言参考手册，希望能帮助大家学习和设计-VHDL Language Reference Manual, hoping to help people learn and Design
Synopsys_Tutorial
- this is good document describing the synopsis tutorial
FPGA
- 一篇比较实用的论文，基于FPGA的视频监控-Paper a more practical, FPGA-based video surveillance
jianpansaomaio
- 基于FPGA开发的键盘扫描程序，适合初学者更好的了解FPGA。-Keyboard scanning procedures based on the FPGA development, suitable for beginners to better understand FPGA.
Vivado 2016.1 安装流程
- Vivado是 Xilinx新一代针对7系列及后续 系列及后续 FPGA 的开发平台。 Vivado 2016.1是官方首个支持 是官方首个支持 win10的版本。(Vivado is the new generation of Xilinx for the 7 and subsequent series and subsequent FPGA development platform. Vivado 2016.1 is the official first support, is the of
CounterUni
- Universal counter written on VHDL in Quartus II. It counts up and down by taking into account overflow and onderrun bits.
ps2_lcd
- PS2_LED，硬件描述语言VHDL，代码简洁，功能完善-PS2_LED, hardware descr iption language VHDL, the code simple and functional. .
timing_constraint
- 主要介绍xilinxFPGA时序约束的方法和技巧。FPGA开发人员进一步提高的必看资料。-XilinxFPGA timing constraints introduces methods and techniques. FPGA developers to further enhance the information of the must-see.
lattice_ddr_verilog-for-orca4
- 莱迪思的DDR控制器源码（包括仿真与说明文档），DDR为MT46V16M8，Verilog-The DDR controller source of Lattice (including simulation and documentation), DDR is MT46V16M8, Verilog
zuihou
- 数字时钟，有校正、闹钟、复位灯一些功能-Digital clock, correction, some of the features of the alarm clock, reset lamp! ! ! ! !
seconds-counter
- 在EP2C5T144C8开发板上编的一个VHDL源程序，相当于一个秒表，读数可在4个数码管上显示，通过按键可暂停计数，可继续计数-In EP2C5T144C8 development board this a VHDL source code, the equivalent of a stopwatch, reading on the four digital tube display, can suspend count by buttons, can continue to count