资源列表
SIN_NEW1Hz
- 正弦波信号的产生,频率为1Hz,FPGA处理模块各部分所需工作时钟信号由输入系统时钟信号经分频得到，系统时钟输入端应满足输入脉冲信号的要求-generte sin wave, the frequence is 1Hz,FPGA processing module is required to work various parts of the system clock signal from the input clock signal by dividing the system clock
DE2_70_TOP
- 在quartus上实现电子锁的设计，采用cyclone的板子，方便设置初始密码，更新密码-Quartus to achieve in the design of electronic locks, using cyclone of the board, easy to set the initial password, update password
beipingqi
- 基于cd4046的倍频器的设计，可以实现1到10khz的倍频-Cd4046-based frequency doubler is designed to achieve a multiplier to 10khz
LCD12864显示汉字
- 利用LCD1864显示FPGA数据，可以作为底层驱动(Using LCD12864 to display the data of FPGA,you can make it be your driver;)
VMMing_Testbench_by_Example
- 基于VMM的验证实例，描述了对一个fifo的验证平台-a systemverilog testbench for vmm
rs
- RS(255,239)verilog代码，已通过quartusII仿真，满足设计要求，需要的可以拿去参考-RS (255,239) Verilog code, through quartusII Simulation meet the design requirements, the need to take reference
RS(255 239 )编码器 Verilog HDL 实现
- 对于 RS 编码器的设计，常用的编码算法有 2 类，一类是 Berlekamp 算法，另一类是典型编码算法。Berlekamp 算法常用于数据速率要求不是很高的环境下，而典型编码算法具有电路实现结构简洁，占用硬件资源少等优点，因此，采用典型编码算法来实现编码器。
FPGA_DE2_MUSIC
- 基于FPGA的乐曲硬件演奏模块设计，利用硬件描述语言设计符合技术指标的乐曲硬件发生模块，建立实验模型，通过电路仿真和下载硬件测试，在DE2 EDA实验平台上验证其功能-FPGA-based music performance modular design of hardware, using hardware descr iption language designed to meet specifications of the piece of hardware modules occurs,
lab4showTAs
- 4 seg display, button debouncer, and controller for parking meter
DSP_Builder
- DSP Bulider入门资料。适合初学者入手-the DATA of TI dsp bulider ,this manul can use for primier hander,and you can master dsp bulider fasterly
ARM32
- 这是一个quartus编写的arm结构的桶形移位器，可以进行移位运算。-This is a the quartus write the arm structure of the barrel shifter, can shift operation.
sdram_access
- sdram 控制器，VHDL程序源代码。-sdram controller,vhdl program