资源列表
DF2C8_03_NixeTube
- ：8 个数码管从 0 开始计数，每次增加 1；每位显示的字符包括从 “0~F”16 个十六进制数； 按下复位按键之后，计数从 0 重新开始。由此可验证数码管、有 源时钟和复位按键等功能。-: 8 digital tube starts counting from 0, for each increase of 1 each displayed character from " 0 ~ F" 16 hexadecimal numbers press the
UART
- 基于FPGA的UART设计，包含接收模块，发送模块，FIFO模块-UART FPGA-based design, including the receiver module, sending module, FIFO module
Second_Counter
- 这是一个四位的数字秒表，精确到0.01秒，三个按键，三个按键，一个复位，一个开始，一个停止,在Digilent的basys2开发板上运行，只须修改ucf约束即可在其他FPGA开发板上运行。-This is a four-digit digital stopwatch, accurate to 0.01 seconds, three buttons, three buttons, a reset, a beginning, a stop, run Digilent' s basys2 dev
DSP_DESIGNING-FOR-OPTIMAL-RESULTS
- Xilinx FPGA内部DSP的最佳设计结果详细介绍。-The best internal DSP Xilinx FPGA design results in detail.
clock3
- 一个带闹钟的分为12 和24 小时的数字时钟。只有24小时有闹钟，都是原件例化，用的是位置关联-With alarm clock into a 12- and 24-hour digital clock. Only 24-hour alarm, all of the original case, the location associated with the
vivado_init
- 该程序是为vivado初始化和配置，并且还包含有相应的说明文档，是初学xilinx vivado的很好的教程，本例程基于zynq系列的MIZ701N处理器进行开发(The program is vivado initialization and configuration, and also contains the corresponding documentation, is a good beginner Xilinx vivado tutorial, this routine based
CLOCK
- 时钟，带闹钟设置，整点报时功能，闹钟带有停止键(Clock, with alarm set, the whole point timekeeping function, alarm clock with stop button)
RD1008
- Receiver module design i am uploding it thax
CAST_sdr_sdram_ctrl-xact
- Single Data Rate Mobile SDRAM Controller Core with AHB Interface
wnl
- 该程序是关于FPGA的万年历程序，程序简洁明了，适合fpga学习者的参考-The program is a calendar program on the FPGA, the program concise reference for fpga learners ..
pll.rar
- 模拟锁相环（apll）的一些simulink模型,Analog phase-locked loop (apll) some simulink model
I2C控制核
- I2C控制核设计,由VHDL语言编写,使普通I/O端口实现I2C性能-I2C control of nuclear design, VHDL language, I / O ports I2C Performance