资源列表
FIFO
- 三种同步方式实现的FIFO，verilog HDL，FPGA，更好理解FIFO-The three implemented synchronously FIFO, Verilog HDL, FPGA, a better understanding of the FIFO
SPI8
- Interface control registers of a FPGA through a SPI bus
caacc
- cavcl entorpy coding
FMS-Labor-3
- MICarrayWeights and MICarrayplot
MAC网络控制的物理层控制程(VHDL)
- MAC网络控制的物理层控制程(VHDL)(The physical layer control of MAC network control (VHDL))
_uart_test2
- data transmitted from FPGA to PC using COM PORT version 2
AXI-full
- axi协议中的full子协议，可用于直接访问zynq器件的ddr器件。(The full sub protocol in the Axi protocol can be used to direct access to the DDR device of the zynq device.)
ambo2000
- AMBE2000芯片的控制，和编码方式控制，码率的控制，成熟的可配置的控制模块。(AMBE2000 chip control and coding control, rate control, mature and configurable control module.)
i2c_slave
- I2C从机模块，支持多种I2C模式，稳定成熟，方便使用。(I2C slave module supports multiple I2C modes, which is stable, mature and convenient to use.)
触发器
- 一个简单的触发器，用于eda实验和电子技术综合实验(A simple digital trigger)
分频器
- 对频率实现分频，达到一种对外部的一种分频管理(realization of frequency division)
tx
- 一个用verilog实现的HDMI发送器，已在XILINX的7系列FPGA上验证(A HDMI transmitter implemented by Verilog has been verified on XILINX's 7-series FPGA)