资源列表
reed_solomon_decoder
- Reed Solomon Decoder written in Verilog Libero core generator.-Reed Solomon Decoder written in Verilog Libero core generator.
fir_16
- fir低通滤波器 用于dspbuilder pll：25ns data 400khz sin 10.8khz
FPGA_SPI_VHDL
- 串行外设接口（SPI）fpga 被动接收,在下降沿 采集数据并发送数据 1BYTE,要求mcu在末端采集数据。并在下降沿之前准备好数据。-Serial Peripheral Interface (SPI), The fpga passive receiving, at the falling edge of data collection the send data 1BYTE, mcu data collected at the end. And the data ready before t
rs232
- verilog语言编写，RS232通讯程序设计-verilog language, RS232 Communication Program Design
SDRAM
- 用Verilog写的SDRAM测试程序。先向SDRAM里面写数据，然后再将数据读出来做比较。-Written using Verilog SDRAM test program. Xianxiang SDRAM write data inside, and then read out the data for comparison.
a10
- I2C总线控制器的VHDL设计及实现 -I2C Bus Controller Design and Implementation of VHDL
kechengsheji
- 基于VHDL语言的一款功能很好的整点报时计时系统。-VHDL language features based on a very good time the whole point timekeeping system.
DAC0832
- 用数模转换器DAC0832和单片机实现了，产生锯齿波得功能。本程序已经通过调试，真是可行。-MCU with digital to analog converter DAC0832 and the produce was sawtooth function. This program has been through debugging, really feasible.
New-Text-Document
- System will fdsdCADL
pipeline
- 以Verilog撰寫而成的Booth’s Algorithm Multiplier，並以Pipeline方式實現。-Written in the Verilog Booth' s Algorithm Multiplier, and the Pipeline way.
source7-8
- verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，7-8章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 7 - 8