资源列表
verilog1602
- 终于搞定了这个lcd液晶显示的程序，净是犯些不该犯的错误，还本人找了那么久，先是仿真查了所有时钟信号，又查了lcd_rs和lcd_rw，都没有错-Finally fix the LCD program, clean is a hideous make some stupid mistakes, I look for so long, the first looked up all the clock signal, and checked lcd_rs and lcd_rw, all not w
BCHdecode
- BCH(63,56) decode,verilog
NiosII-example
- NIOSII电路设计 ，经典的实例祝你在学习中更准确的掌握工作中实用的技术！-NIOSII circuit design, classic examples I wish you a more accurate grasp of the practical technical work in learning!
66_FIR
- 这是一个VHDL写的FIR模块，我的编译环境是QuartusII 5.0-This is a VHDL modules written FIR, I compiler environment is Quartus II 5.0
HW_songer_yijianmei
- 用VHDL编写的播放器，播放一剪梅主题曲之《一剪梅》，另附编码表WORD档-Using VHDL prepared player,一剪梅play the theme song of
NIOSII_tutorial_code
- NIOSII实例代码。包括系统时钟代码，DMA(Memory to Memory)驱动代码，Fine-gained Flash Access驱动代码,Timestamp驱动代码,ISR代码，Simple Flash Access驱动代码，UART代码
VGAzifuxianshi
- 用VERILOG编写的VGA字符显示，可以在电脑屏幕上显示字符,已通过测试-Prepared with the VERILOG VGA character display, can display characters on a computer screen, has been tested
FPGA
- 韩福柱老师FPGA实验源码，用vhdl语言在xilinx FPGA上实现，包括ad采集，温度传感器读取，秒表，跑马灯和按键次数统计4个实验-Han Fu teacher FPGA column experiment source code, vhdl languages on xilinx FPGA implementations, including ad acquisition, temperature sensor readings, stopwatch, marquees and key
vhdlsample
- vhdl program for bcd conter to 7 segment display
sramfiles
- interface on virtex test ram
ps2_mouse_231908867
- cyclone II芯片 鼠标读写控制-cyclone II chip to read and write control mouse