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资源列表
prog_complet
- it is a program in VHDL of a multiplier
1
- 实现彩灯功能，用verilog实现。语言简单-Lantern features to achieve
adder4_1
- 这是用vhdl编写的四位加法器，请多指教-this is the preparation of the four VHDL Adder, please enlighten
nand
- ABOUT NAND GATE VHDL CODE
Uart
- FPGA verilog UART串口通信,可通过RS232串口与串口助手通信。-FPGA verilog UART communication, it could connect with UART assistor with RS232 port.
adc_ads7842
- 由system verilog编写的adc_ads7842的驱动模拟程序-Adc_ads7842 verilog prepared by the driving simulator
CHWCNTACORA
- VHDL编程语言设计，显示灯，显示VHDL字样。-VHDL programming language design, indicator lights, indicating the word VHDL.
q_rom.xcp
- dESIGN THE ROM ENCODER FOR jpeg
counter-interrupt-8-timer-04s
- 单片机源程序（keilC语言）---计数器中断8次定时04s件，不需编程，但仅是对霍尔传感器测速应用的验证。-SCM source (keilC language)--- counter interrupt 8 timer 04s
Promediador
- This a Promediator for the Altera DE2-2 it use a looktable for obtein the data and then promediates the current sample with 3 past samples.-This is a Promediator for the Altera DE2-2 it use a looktable for obtein the data and then promediates the cur
displayCounter2.tar
- Verilog example of a program that uses a 7 segment display (included in fpga) to display a counter 0 to 99. Implemmented in FPGA Nexys3-Verilog example of a program that uses a 7 segment display (included in fpga) to display a counter 0 to 99. Imple
mips
- mips pipeline code.. copyright material for fr-mips pipeline code.. copyright material for free