资源列表
uart_lcd
- 基于FPGA的UART通信，并用LCD(1602)显示通讯状态和通讯的数据。通过在ALTERA公司生产的DE2-115开发板上运行，证明此程序稳定可靠。时钟为50MHz，语言为VHDL,状态机。-FPGA-based UART communication, and LCD (1602) show the communication status and data communications. DE2-115 development board by ALTERA Company product
edashuzipinlvji
- EDA/VHDL数字频率计，可编程逻辑门阵列，EDA课程设计-EDA/VHDL digital frequency meter, programmable logic gate array, EDA curriculum design
CopperHoleTest3.17
- 一个简单的状态机，用来实现一个操作流程和8段码的显示及老化控制-A simple state machine, used to implement the display of an operation process, and 8 code
FULL
- Full code for fused floating point operations.
ADD_UNIT
- floating point add unit
SUB_UNIT
- floating point subtract unit
ADD_SUB
- floating point fused add-subtract unit
DE2_115_Audio
- DE2-115开发板音频录放verilog HDL代码-DE2-115 development board audio recorders verilog HDL code
DE2_115_NIOS_DEVICE_LED
- DE2-115开发板的LED灯设计 Verilog HDL语言编写-DE2-115 development board LED lamp design Verilog HDL language
DE2_115_NIOS_HOST_MOUSE_VGA
- DE2-115开发板的verilog HDL的VGA设计-DE2-115 development board VGA verilog HDL design
DE2_115_PS2_DEMO
- DE2-115开发板的PS2的Verilog HDL语言设计-The DE2-115 development board of the PS2 Verilog HDL language design
xapp1015
- SDI接口的VHDL实现，XILINX官网的设计参考-SDI interface VHDL realize XILINX official website design reference