资源列表
fpga_dsp_simple
- dsp和fpag通信的测试程序，包含整个工程和signaltap测试信号。-the the dsp and fpag communications test procedures, including the entire the engineering and signaltap test signal.
hanshufashengqi
- 设计一个函数发生器，用VHDL语言实现。可以实现正弦、余弦等多种函数的波形-Design a function generator using VHDL. You can achieve a variety of functions such as sine, cosine waveform
Ex11_LCD1602
- FPGA LCD1602 VDHL源码-FPGA LCD1602
duoweishumaguan
- 通过该程序可是用矩阵键盘实现对多位数码管的控制，让多位数码管显示想要的数字，智能方便。-Through the program but realize the control of the number of digital tube with the matrix keyboard, make a number of digital tube display to digital, intelligent and convenient.
DIV
- 奇偶分频，输入方波信号与分频系数，则输出分频后方波-Parity divider input square wave signal with the frequency division factor, output frequency division behind the wave
lcd
- LCD_1602(VHDL）显示自定义字符“贾”，显示通讯状态“send”和“recieve”，状态机，结构简单易读稳定，非常适合初学者。此程序已在altera开发板运行成功。-LCD_1602 (VHDL) custom character " Jia" , the communication status " send" and " recieve the state machine, easy-to-read structure stable, v
synchronism_design
- 信号进入不同时钟域时的同步处理的例子，请有需要的借鉴参考-Example of the synchronization signal into different clock domains, there is a need to draw reference
Timing-Analysis
- 关于VHDL/VERILOG进行EDA设计时序分析时需要注意的一些需要注意的问题及处理策略，保证相当实用，请需要的人参考-VHDL/VERILOG the EDA design timing analysis need to pay attention to some issues that need attention and treatment strategies, guaranteed to be quite practical, please need Reference
uart_fifo_design
- verilog语言时序的异步读写FIFO，请需要者借鉴参考-the verilog language Timing asynchronous read and write FIFO, for those who need to learn from reference
FFT-transform
- 64位FFT变换源代码，仅供参考。此为单一模块文件，自行建立工程编译-64 FFT transform source code, for reference only. This is a single module file, create your own works compiled
Verilog
- 实现对文本的检测，实现关键字的过滤，开发工具 ISE14.1以上
Lab07
- LabVIEW FPGA Implementation of Convolution