资源列表
SystemVerilogEventRegionsRaceAvoidanceGuidelines.r
- The IEEE1800 SystemVerilog Standard includes new event regions primarily added to reduce race conditions between verification code and SystemVerilog designs. The new regions also facilitate race-free Assertion Based Verification (ABV). This pap
Vote7
- 源码，内容是用VHDL语言编写的7人表决器-Source code, the content is written in VHDL voting devices 7
Adder4
- 源码，内容是用VHDL语言编写的四位全加器-Source code, using VHDL language of the four full-adder
74LS160
- 源码，VHDL语言编写的74LS160计数器-Source code, VHDL language of the 74LS160 counter
bianbuchangjiajiancount
- 源码，VHDL语言编写的可变步长加减计数器-VHDL language variable-step addition and subtraction counter
maikuantiaozhifashengqi
- VHDL语言编写的正负脉宽数控调制信号发生器-VHDL language of the positive and negative pulse-width modulated signal generator NC
yingyuzimuxianshi
- 用VHDL语言编写的英语字母显示电路，经过验证-VHDL language with the English alphabet display circuit, proven
FPGA
- FPGA设计指南：器件、工具和流程 一本好书，介绍FPGA的基础知识。-FPGA Design Guide: devices, tools and processes, a good book to introduce the basics of FPGA.
VHDL_CXSL
- vhdl 讲解，扫描版PDF VHDL_CXSL-vhdl explain, scan version PDF VHDL_CXSL
dfdfd
- hello fpga project hello fpga project-hello fpga project hello fpga project hello fpga project
Verilog-DRAM
- fpga(veriloh hdl)编写的SDRAM程序说明 -fpga(veriloh hdl)SDRAM
SRAM_2
- fpga(veriloh hdl)编写的SDRAM程序 -fpga(veriloh hdl)SDRAM