- random Visual c++产生随
- 3GPP_Tutorials_01_Layer1_General_Description This an internal tutorial material from one european company. this document is about the physical layer. I will continue to upload all the training material.
- stoneagePICchange.exe11 用于读取
- deerees 窗口
- connectWithStream 利用socket网络编程和图形界面技术
- baoming-V7.8 Acquisition and Processing of the speech signal
资源列表
ciper
- VHDL语言，基于Xilinx平台的电子密码锁。-VHDL language, based on the Xilinx platform of electronic locks.
SRAM_selfcheck_READ_SRAM
- 用来检测sram是否正常工作的简单测试程序，欢迎大家下载使用-Sram is working properly to detect a simple test program are welcome to download
an484_CN
- 用MAX II CPLD，通过SMBus 实现GPIO 引脚扩展-With the MAX II CPLD, achieved through the SMBus pin GPIO expansion
divtest
- VHDL数字锁相环所用的分频器，需要的同学可以试一下。-fenpinqi
for_ws
- 裡頭有加法器,全加器,rippple adder-full adder ,rippple adder
RA
- ripple adder 程式撰寫,此利用verilog撰寫-ripple adder
adder
- 加法器程式設計,這是利用verilog寫的-adder
add_16bits
- 這是16bits加法器,利用verilog程式撰寫-adder-19bts
uart
- FPGA中的UART模块，调试通过的哦！！希望对大家有所帮助，呵呵。。。我用的是quartus7.2版本编写的，当然也有些copy网上的-FPGA in the UART modules, debugging through the Oh! ! We want to help, Hehe. . . I use the quartus7.2 version of the written, of course, also some copy online
VerilogExample
- 此文件包含大量的verilog例程，对学习很有帮助。-verilog example
frehp
- 基于频率抽样方法实现Ⅰ型FIR数字高通滤波器-Based on the frequency sampling method to achieve type Ⅰ FIR digital high-pass filter
xb
- 用汉宁窗设计一个FIR高通数字滤波器，满足以下参数要求：通带边界频率ωp=0.7π，通带内衰减函数αp=0.4dB；阻带边界频率Ωs=0.4π，阻带内衰减函数为αs=55dB。-With the Hanning window design an FIR high-pass digital filter to meet the requirements the following parameters: passband edge frequency ωp = 0.7π, pass-band at