资源列表
DDS
- 基于FPGA的DDS详细设计方案（附带详细设计方案及代码）-DDS-based FPGA detailed design (with the detailed design and code)
DIFF
- 基于FPGA的DIFF详细设计方案（附带详细设计方案及代码）-FPGA-based DIFF detailed design (with the detailed design and code)
7_lan
- 黑金开发板ENC28J60的Nios驱动-Black gold ENC28J60 development board driver
FPGA_multiplier
- 本源码是用verilog语言编写的FPGA乘法器，可以输入两个8位数据，出输16位结果。-The source code is written in verilog FPGA multiplier, you can enter two 8-bit data, the output 16 results.
FPGA_SPI
- 本源码是用verilog语言编写的FPGA的SPI主机代码，可以用做SPI开发参考。-The source code is written in verilog FPGA SPI master code, can be used to develop a reference SPI.
FPGA_Divider
- 本源码是用verilog语言编写的FPGA的除法器和74LS138及D触发器模块。-The source code is written in verilog FPGA divider and 74LS138 and D flip-flop modules.
FPGA_8bitLED
- 本源码是用verilog编写的FPGA程序，其中包括了7段数码管显示模块和8位转换器。-The source code is written in verilog FPGA program, including 7-segment LED display module and 8-bit converters
paobiao
- 本源码是用verilog编写的FPGA程序，其中包括了数字跑表模块和RS触发器模块。-The source code is written in verilog FPGA programs, including digital stopwatch module and the RS flip-flop modules.
ASIC
- 西安交大asic课件，对于数字集成电路的学习有帮助，经典-Xi' an Jiaotong University asic courseware for learning to help digital integrated circuits, classic
dds
- ad9910 使用方法的论文，用于调频源设计，-AD9915 PAPERS， to jumping frequency
smg_99
- 运用verilog，控制数码管从1开始计数到99，希望在这里和大家一块学习交流-Use verilog, control starting from 1 to 99 digital tube, hope and everyone here a study and communication
flowlight
- vhdl编写的流水灯，即多个发光二极管轮流亮灭-it s a flowlight in vhdl