资源列表
ppm_tb
- PPM编码器的测试文件，可以测试PPM编码是否正确-PPM encoder test file, you can test whether the correct PPM encoding
aib-01017-soc-fpga-overview
- Altera SOC platform overview for Stratix-V, ArriaV FPGA families, with ARM Cortex A9 Dual COre Hard Macro embedded. This is a seminar document, attended in May 2013
Altera_SoC_seminar
- Altera SOC Seminar November 2012
乘法器
- 乘法器的源代码，以及其测试文件，testbench，是word的形式
饮料售货机verilog
- 设计一个自动售货机系统，每份5分钱的饮料，只能投1分、2分、5分硬币，要求正确地找回钱数。
digital-clock
- 基于FPGA的数字时钟设计，时钟可以按设定好的时间进行自动计时，FPGA板子上可以显示相应的时钟数字，是数字电路课程的一个课程设计，也是对于VHDL语言的一个熟悉过程.-FPGA-based digital clock design, the clock can be a good time to set automatic timing, FPGA board clock can display the corresponding figure is a digital circuit des
digtal_clock
- FPGA实现数字钟VHDL语言编写,包涵整点报时，清零，调时调分等功能-FPGA digital clock VHDL language, includes the whole point timekeeping, cleared when the transfer function of adjusting grading
fpgaaixin
- fpga实现爱心，verilog语言编写，采用的是cylone2系列的芯片-fpga implementation of love, verilog language, uses a series of chips cylone2
uart-to-GPIO.vhd
- -- Filename ﹕ uart.vhd -- Author ﹕ZRtech -- Descr iption ﹕串口接收与发送程序 -- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证-- 程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位-- 8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波-- 特率。程序当前设定的div_
Test9454
- S3F9454控制芯片仿真器测试程序，可验证仿真的可行性-S3F9454 control chip emulator test program that verifies the feasibility of the simulation
sd_card_controller_latest.tar
- The SD Card Controller IP Core is MMC/SD communication controller designed to be used in a System-on-Chip. The IP core provides a simple interface for CPU. The communication between the MMC/SD card controller and MMC/SD card is performed accord
MGC-07-H
- OPENice-i500仿真器验证实例，很实用，方便开发和验证-OPENice-i500 emulator authentication instance, it is useful to facilitate the development and validation