资源列表
fpga_fenpin
- 这个是根据fpga芯片写的分频模块，modelsim综合，QuartusII测试-This is the fpga frequency module, modelsim comprehensive, QuartusII test
state_machin_VHDL
- Introducing BB FlashBack BB FlashBack is a screen recorder - it makes movies of what you see on your PC screen.
Fpga_post_synth
- vhdl code for Fpga_post_synth
InternalProgramMemory
- vhdl code for InternalProgramMemory
Timers
- vhdl code for Timers in 8051
vhdl
- vhdl code for serial_receiver
EDA
- Verilog语言入门,同时加强对EDA的学习-VerilogStudent learn
bcd
- 这是一个在vhdl中BCD的编程代码 为了可以让它更直观的表现出来 我们最后用7seg的方式 让其表示出来 把结果更加直观的呈现-This is a BCD in vhdl programming code in order to be able to make it more intuitive performance out of our way to let it finally 7seg represented more intuitive presentation of the res
jk-filpflop
- 这个是vhdl中很常见的jk filpflop的文件只用于很小数位的变化 其中的jk文件是up down运算都符合的-This is a very common vhdl jk filpflop file is only used for very small changes in a digital file which jk is up down operations are met
Add_Sub_4_Bit
- 这个是vhdl中很简单并且很基础的adder减法编码 主要是为以后的学习ram编码做准备 其中包括fulladder和halfadder-This is a very simple and very vhdl based adder coding is mainly for future learning ram preparation including fulladder coding and halfadder
multi
- 这个只是在vhdl中符合4bit adder的乘法code内带test 可放心使用都是小弟已经检测过的-This just in line with 4bit adder vhdl multiplication code can be freely used within the zone test are brother had been detected