资源列表
shift_reg
- Shift Register VHDL program developed in Modelsim
sipo
- Serial In Parallel Out Shift Register in VHDL in Modelsim
vhdl3
- Various VHDL programs written in Modelsim
vhdl4
- Various VHDL Programs developed in Modelsim
mp3_designtest
- MP3 player source code
reed_solom
- REEDSOLOMON source code
rs232_syscon_latest[1].tar
- RS232 Controller with baudrate generator of 1152-RS232 Controller with baudrate generator of 115200
spislave_latest[1].tar
- Serial Peripheral Interface Slave interface
8b10b_encdec_latest[1].tar
- Serial peripheral interface for M68HC11 compatible
spi_latest[1].tar
- serial peripheral interface master interface Wishbone compatible
CDMA_MULT3_ise9migration
- CDMA Source code and documentation
PSEUDO_RANDOM_ise9migration
- Pseudo Random Generator source code