资源列表
devider
- 分频器 可以实现1：3 1：1 的分频器 源代码-Divider can achieve 1:3 1:1 divider
PPM
- PPM 编码器 能实现相关编码功能 内附仿真文件和仿真报告-PPM encoder encoding function to achieve the relevant documents containing simulation and simulation reports
cpu
- RIsc 处理区 内附仿真文件和相关报告-RIsc treatment area containing a simulation files and related reports
wkt
- 交通灯源码-traffic light controler
tft_lcdPili9325
- tft驱动，放心使用吧，经过测试已经是完好的了，如假包换-TFT driver, feel free to use it, after the test is in good condition, such as the original
zynq_led_show
- 在PlanAhead和SDK14.4上做的一个Zynq-7020的小程序，旨在熟悉开发环境和流程。-On the PlanAhead and SDK14.4 do a small program Zynq-7020 is designed to be familiar with the development environment and processes.
2stOTA
- 带米勒补偿效应的二级运算放大器实现电路图，CMOS-Two operational amplifiers with Miller compensation effect achieved schematics, CMOS
2stageMillerC2012v6
- 带米勒补偿效应的二级运算放大器实现电路图，在Hspice中实现的代码-Two operational amplifiers with Miller compensation effect achieved schematics, code implemented in Hspice
tb_asy_fifo
- the testbench of asynchronous fifo-test the logic function of asynchronous fifo
vhdl_lcd_12_17
- 用vhdl语言编写的lcd显示程序,程序经过下载验证-Lcd display with vhdl language program, the program after downloading verification
EDAlabor3
- 半加器到全加器，8421码到geleima转换。-Half adder to full adder, 8421 yards to geleima conversion.
singleCPU
- 用Verilog实现的单周期CPU,分别实现I型、R型、J型指令，并包含测试文件。可供参考。-With single-cycle CPU Verilog implementation, respectively, to achieve type I, R, J-type instruction, and includes test files. For reference.