资源列表
ADC_AMP
- VHDL code for ADC on Spartan 3E starter kit
game
- 小游戏规则： led(0 to 3)是按一定规律不断发亮，每次只有一个灯亮，每个灯都和我们BASYS板上的四个按钮中的一个对应着，当Led(0 to 3)中的灯亮时，我们要按对相应的按钮时候，在led(4 to 7)中对应的按钮就会亮起，并且八段码显示的数字也相应的加上一，要是按错了led（4 to 7）灯不亮，且显示数字减1。-A small game in which LED(0 to 3) lights in turn. Just one LED turns on each tim
crc_accelerator
- CRC 的Nios的软核处理，系统采用Altera Nios IP核进行CRC算法，算法运行时间比常规CRC校检节省很多。-CRC' s Nios soft-core processing, the system uses Altera Nios IP core for CRC algorithm, algorithm running time than the conventional CRC checkout save a lot.
8051_verilog
- 8051 IP, 使用veriog实现，在Altera9.0环境下编译通过-8051 IP in verilog, which is verified in Altera9.0 environmen.
PS2
- PS2键盘读取程序，直接调用PS2.h中的函数即可。在main函数中有详细的例程。非常好用-PS2 keyboard reading program, a direct call to the function can be PS2.h. In the main function of the routine in detail. Is very easy to use
OCMJ_LCD
- 超大液晶显示程序-金鹏0CMJ15X20D系列。MSP430上验证通过。-Large liquid crystal display programs- Jinpeng 0CMJ15X20D series. Verified by the MSP430.
oscillograph
- 用VHDL编写的oscillograph数字部分源代码，在Altera FPGA上跑通。直接把模拟部分输入输出AD，DA信号接入本模块即可。-Digital oscillograph with the written part of the VHDL source code, in the Altera FPGA on the run-pass. Directly to the analog input and output AD, DA signal can access this modul
irq_decoder
- 中断优先编码器的描述，输出中断向量供CPU读取，非常好用，只要稍稍修改，就可以产生您所需要的中断向量。-Descr iption of interrupt priority encoder, the output for the CPU interrupt vector read, very easy to use, if slightly modified, it can generate interrupt vector you need.
simple_pic
- 一个通用中断系统的Verilog HDL描述，对想了解知道是怎么实现的读者，可以查看综合出来的电路，会有很大帮助！-A common interrupt system of the Verilog HDL descr iption of the would like to know how to achieve the readers know, there will be of great help!
keyscan
- 2×8 键盘扫描编程--- VHDL语言-2×8 keyboard scan---VHDL language
80C51_1
- 1.异步通信软件模拟2.基于RS-232的串口通信3.基于RS-485的多机通信4. I2C总线协议的软件实现5. SPI总线在单片机系统中的实现6.-wire-1. Asynchronous communication software simulation 2. Based on the RS-232 serial communication 3. Based on the RS-485 Multi-machine communication 4. I2C bus protocol soft
Verilog_VHDL_Golden_Reference_Guide
- Verilog source code is usually typed into one or more text files on a computer. Those text files are then submitted to a Verilog compiler or interpreter which builds the data files necessary for simulation or synthesis. Sometimes simulation imm