资源列表
paobiao
- 该程序是用verilog语言实现的数字跑表功能，其中分为计数模块与数码管显示模块。-The program is verilog language digital stopwatch function, which is divided into counting module with digital display module.
AudioSubSystemStereo
- DE2-115 AUDIOSUBSSTEM
key_scan
- FPGA键盘扫描，采用VHDL语言编写的键盘扫描代码-FPGA keyboard scanning, the use of VHDL language keyboard scan code
keyboard4_4
- 4X4矩阵式键盘的VHDL语言程序 FPGA-Keyboard VHDL language 4X4 matrix program
DAC
- DAC spartan 3e starter
NCO
- 是数控振荡器的程序，能够产生正弦和余弦信号，是上、下变频技术的主要步骤-NCO of the program is capable of generating sine and cosine signals, is on the main steps of down-conversion technology
Verilog-interface
- 基于fpga的verilog语言 实现的串口接收发送数据编程-fpga serial
router_routing
- 片上网络NOC基于fpga实现的，routing模块。-NOC-chip networks realized fpga-based, routing module.
FIR-LOOP-
- 数字接收机中的FIR滤波器，环形滤波器设计参考,VHDL代码-the FIR filter， loop filter design in a digital receiver,vhdl code
jiaotongdeng
- 交通灯绿灯先亮60s，黄灯闪烁10s，红灯亮60s，交替循环。-The traffic lights first 60 s bright green, yellow lights flashing 10 s, 60 s red light, cycle.
Exp1_Part234
- Altera Exp1_Part2,3,4 for DE0
DPRAM
- 利用vhdl编写的双端口Ram程序，不带数据纠错处理