资源列表
flash_cont
- FLASH_CONT Parallel FLASH Memory Controller
uart_altera
- EPM3128与PC机进行串口通讯。使用VHDL语言描述了RS232C的信号传输过程。-EPM3128 and PC for serial communication. Using VHDL language describes the RS232C signal transmission process.
I2C_EPM3128
- EPM3128 与EEPROM的读写。EPM328用VHDL语言描述了I2C总线。-EPM3128 and EEPROM read and write. EPM328 uses VHDL language to describe I2C bus line.
DDS
- DDS control system. it controls the chirp of the AD9854.
sr_flip_flop.ZIP
- I upload a source code for SR flipflop here.
VHDL_4bit_magnde_compar_code_testbench
- this a vhdl testbench for a 4 bit magnitude comparator that comprises all the stimuli a 4 bit magnitude comparator function table.-this is a vhdl testbench for a 4 bit magnitude comparator that comprises all the stimuli a 4 bit magnitude comparator
VHDL_4bit_magnde_compar_code_dataflow
- this is a source code for a 4 bit magnitude comparator using dataflow technique a 4 bit magnitude comparator logic circuit.-this is a source code for a 4 bit magnitude comparator using dataflow technique a 4 bit magnitude comparator logic circuit.
float_point_divide.tar
- this project divide two floating point number.
ALU-Design
- 8 bit alu design features: optimized design inclusive of multiplier
shizhong
- VHDL设计带报警的59分钟定时器，系统以秒速度递增至59分钟后,启动报警1秒钟,置位后又以秒速度递减至零并报警1秒钟。-VHDL design with alarm 59 minutes timer
mux
- This file is about mux in ISE by VHDL language.
Han-carlson.ppt
- Abstract—Variable latency adders have been recently proposed in literature. A variable latency adder employs speculation: the exact arithmetic function is replaced with an approximated one that is faster and gives the correct result most of the time,