资源列表
sequential
- this a sample of sequential circuit in verilog and VHDL-this is a sample of sequential circuit in verilog and VHDL
Combinational
- this is a sample of combinational circuit in Verilog and VHDL. such as multiplexer, decoder, adder etc
simplever
- this simple code to understand and, or and top level-this is simple code to understand and, or and top level
chuanxing
- VHDL的串行通信程序,硬件描述语言，使用xilinx ISE软件-VHDL serial communication program
pwm
- VHDL, quartet 2 , FPGA, cyclone II, controllen PWM brightness
simwindfarm-v1.0
- GFH GFH DFHFDHD GHDHFDHHFD DFHFDHDF-GFHGFHGFH DFHFDHD GHDHFDHHFD DFHFDHDF
dac_ctl
- 主要功能为控制DAC芯片，来控制压控晶体振荡器，产生所需的时钟信号。-Mainly used for DAC control VCO to generate the required clock signal can be used directly.
OV7670_VGA
- 实现OV7670照相机采集和在VGA显示屏上进行显示，易于理解和学习。-OV7670 camera acquisition and display on VGA display screen, easy to understand and learn.
FTChipID_LV7.zip
- FTChipID_LV7.zip
safe_state_machine_v
- The Verilog HDL Templates for State Machines that included in the Design Example web page are: o 4-State Mealy State Machine o 4-State Moore State Machine o Safe State Machine o User-Encoded State Machine-The Verilog HDL Templates for S
user_encoded_machine_v
- The Verilog HDL Templates for State Machines that included in the Design Example web page are: o 4-State Mealy State Machine o 4-State Moore State Machine o Safe State Machine o User-Encoded State Machine-The Verilog HDL Templates for S
moore_state_machine_v
- moor状态机的示例代码，再次基础上可以学习标准的状态机写法-moor state machine sample code, we can once again learning standards based on the wording of the state machine