- screen1234 简单的屏幕保护 对学习很有帮助 哈哈哈 好好学习吧
- Neural_Network_Src.tar 神经网络的教程代码
- VBAPAO 基于VBA
- ThresholdingOutputStream An output stream which triggers an event when a specified number of bytes of data have been written to it. The event can be used
- QGB 轻骑兵论坛式留言本 v1.0 管理员帐号密码为admin
- unix Unit time stamp converter. Adapting for Vivaldi
资源列表
8b10b_endecode
- 8b转10b的编码和解码程序，已验证。ALTERA官方代码，有编码和解码两个文件-an 8b10b decoder, based on files Martin R and IBM paper
ug480_7Series_XADC
- xinlinx V7芯片 用verliog 和vhdl 实现自带adc的模拟量采集-xinlinx V7 chip with verliog and vhdl realization comes adc analog acquisition
IIR
- IIR滤波器是线性数字滤波器中最常见的一种类型。在一个给定的时间上IIR的输入依赖于它们的输入和先前的输出值。-IIR digital filter is a linear filter is the most common type. At a given time IIR input depending on their previous input and output values.
fifo
- FIFO是通过时钟来确定是同步还是异步的，同步FIFO的读写操作是通用一个时钟来控制的。另一方面。两个不同频率或者不同香味的时钟来控制异步FIFO的读写操作。 异步FIFO 跨越时钟域的同步问题-FIFO is determined by the clock is synchronous or asynchronous, synchronous FIFO read and write operations are a common clock control. on the other ha
eetop.cn_Uvm_spi_bl_reg_tb
- uvm apb verification env
VER_I2C_EEPROM.ZIP
- EEPROM 的verilog仿真模型（cat24cxx系列）-verilog simulition Model of EEPROM,include cat24cxx
lcd
- Sparn3E 开发板，基于FPGA，实现板子上的LCD能够点亮，并且实现字符和 数字的显示-Sparn3E development board to achieve LED lights lit
PICTUR_EFPGA
- 学习FPGA的图像处理资料，需要一定的基础知识看起来才比较容易。-Learning FPGA image processing information, need some basic knowledge it looks easier.
xuexidds
- 利用quartus平台使用verilog语言实现直接数字频率合成-Use quartus platform verilog language Direct Digital Synthesis
UART6
- its a Universal ART code writen by VHDL
zongbian4
- 基于verilog语言的差分曼彻斯特编码，内包含数据的采集，CRC校验（8位），和编码，输出。附有完整的工程文件。可直接调用modelsim仿真。-Based on differential Manchester encoding verilog language, and contains data collection, CRC check (8), and coding. With complete project file. Modelsim simulation can be call
Filterfgfftd
- LIBRARY ieee USE ieee.std_logic_1164.ALL library work use work.fft_pkg.all