资源列表
LCD1602
- LCD1602液晶 用VHDL语言写的显示字符串-LCD1602 LCD with VHDL language to write the display string
top_clock-plus
- 在quartus ii上仿真24小时的时钟在输入基本的时钟信号后，秒数，分数，小时数的变化-After entering the basic clock signal, seconds, fractions, changes in the number of hours of simulation on a 24-hour clock quartus ii
ADC_READ
- 读取 模数转换器的数据 把读来的数据存在FIFI中-ADC read，Einlesen der Daten von ADC-Wandler dann in FIFO Speichern
design
- 浮点数是属于有理数中某特定子集的数的数字表示，在计算机中用以近似表示任意某个实数。-Floating point numbers are rational numbers belonging to a particular subset of the digital representation for an approximate representation of any real number in the computer.
parall_interf
- SPI是串行外设接口(Serial Peripheral Interface)的缩写。SPI，是一种高速的，全双工，同步的通信总线，并且在芯片的管脚上只占用四根线，节约了芯片的管脚，同时为PCB的布局上节省空间-Serial Peripheral Interface
gray_counter
- altera官方格雷码计数器的verilog代码和testbench,已测试-altera official Gray code counter verilog code and testbench, have been tested
UD_DIVDER
- 定制化分频器的verilog源代码，分频器变量已参数化，好用-Customized divider verilog source code, variable frequency divider parameterized, easy to use
pipeline_add
- pipeline式累加器的verilog代码和testbench文件，已验证-pipeline type accumulator verilog testbench code and documents, verified
double_addsub
- 双字的加减法的verilog源代码和testbench，已经过测试-verilog source code and testbench double word addition and subtraction, and has been tested
verilog_uart
- verilog编写的uart源代码，altera官方代码，已验证-verilog prepared uart source code, altera official code, verified
crc
- 用于ethernet的CRC校验源代码，ALTERA官方代码，已验证-CRC checksum of the source code for ethernet, ALTERA official code, verified
X4_8B10B
- 4倍转换率的8b转10b的编码和解码程序，已验证。ALTERA官方代码，有编码和解码两个文件-8b 4 times the conversion rate of turn 10b encoding and decoding procedures have been verified. ALTERA official code, encoding and decoding two files