资源列表
SPI_ADC
- spi串行输出ADC——AD7989的verilog源代码。(Spi serial output ADC - AD7989 Verilog source code.)
bt656_decode
- 将嵌入式BT656格式数据解码出带行场同步信号的YCbCr422格式数据(Decoding Embedded BT656 Format Data to YCbCr422 Format Data with Field Synchronization Signa)
Xilinx
- 2020 XILINX Vivado ISE IP License最全最可靠License获取方式。 LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G Enthernet MAC 40G Enthernet MA
polyPhaseFilter
- 数字信道化过程中多相滤波器组matlab代码及测试(Digital channelized polyphase filter code and test)
CDCM6208_SPI
- 完成对cdcm6208的时钟芯片的配置，输出高频时钟(cdcm6208 cofigure using SPI interface)
PID
- 利用Verilog语言实现PID增量式控制，输出占空比(Using Verilog language to realize PID incremental control and output duty cycle)
sram_ctr
- SRAM VERILOG 实现FPGA控制SRAM的功能。测试可以使用。(SRAM verilog fpga vivado ise quartus.)
AHB5-master
- amba ahb2 协议vip，包括master和slave(AMBA AHB 2.0 VIP in SystemVerilog UVM)
RSC.rar
- Turbo码编码器的两个分量编码器RSC，主要由四个移位寄存器和两个模2加法器组成,Turbo code encoder of the two component encoders RSC, mainly by the four shift register and the two-mode adder composed of 2
rom
- A ROM to build a squaring circuit
wave_generator
- 用VHDL写的波形发生器程序，初学者可以参考下，超经典的-Waveform generator with a program written in VHDL, beginners can refer to, the ultra-classic
halfadder.v.tar
- Verilog Code for Half Adder Circuit with testbench code-Verilog Code for Half Adder Circuit with testbench code...