资源列表
handset
- 利用硬件描述语言vhdl模拟实现与9针ps2手柄的串行通信，完成手柄输入信号的采集。-Vhdl simulation using hardware descr iption language to achieve ps2 with 9-pin serial communication handle, the handle to complete the input signal acquisition.
altera8052
- EP2C5核心电路原理图,包括PROTEL 封装和元件库-无
sopc_builder_tutorial
- This application ready to run about use altera monitor program with de2 sample processor
DDS -changed
- DDS技术实现波形产生代码，可以编译下载学习使用！(DDS generate diagram program)
RS232
- 此代码已在实验板上验证，波特率9600，时钟50MHz。-This code has been verified in the experimental panel, 9600 baud, clock 50MHz.
Verilog-HDL-Synthesis
- 学习如何使用Verilog HDL综合，进行时序分析-Verilog HDL Synthesis A Practical Primer
Verilog_HDL_Synthesis_J_Baskar
- its describes about vhdl code,syntax etc
VerilogHDL_Synthesis
- VerilogHDL_Synthesis_A_Practical_Primer，一本经典的verilog教程，详细介绍了可综合的verilog，对于做硬件的很有帮助-VerilogHDL_Synthesis_A_Practical_Primer, a classic verilog tutorial introduces synthesizable verilog, very helpful for the hardware to do
verilogdesign
- 硬件描述语言设计相关的一些经典文章，包括国外大学的经典教案，和一些设计指导-verilog design
VHDL
- VHDL Sysnthesis book
VHDL_signal
- 运用VHDL基于FPGA的信号控制，进行去抖动等操作，从而实现对功能的控制-VHDL signal
Verilog_HDL_Synthesis_A_Practical_Primer
- verilog综合经典教程，verilog标准制定人写的书，推荐-verilog synthesis classic tutorials, verilog standard-setting people write books, recommended