资源列表
ddr
- ddr2控制器设计,适用于xilinx fpga,内含IP软核 -ddr2 controller design for xilinx fpga, embedded IP soft core
VerilogHDLxiayuwen
- Verilog HDL数字设计与综合 夏宇闻译（第二版）-Digital design and synthesis of Verilog HDL translation of Xia Yu Wen (Second Edition)
led_seq
- 本程序我已经验证过了，没有问题，大家可以放心使用。-The Program I has already been verified, no problem, you can be assured use.
DDR_sdram
- 文件里有DDR3/DDR4 sram的verliog模型，而且具有DDR4参考书(The document has a verliog model of DDR3/DDR4 SRAM, and it has DDR4 reference books.)
iic_v1.0_for_sim
- 程序用于配置ad9883a芯片寄存器，采用iic协议，可以写入后再通过串口输出，方便调试。-The program used to configure ad9883a chip registers, the iic agreement, you can write and then output through the serial port, to facilitate debugging.
AD9883 iic_v1.0_for_sim
- 程序用于配置AD9883芯片寄存器，采用iic协议。 FEATURES Industrial Temperature Range Operation 140 MSPS Maximum Conversion Rate 300 MHz Analog Bandwidth 0.5 V to 1.0 V Analog Input Range 500 ps p-p PLL Clock Jitter at 110 MSPS 3.3 V Power Supply Full Sync Proces
fftinterface
- 电赛一等奖作品：音频信号分析仪的FPGA源码，VHDL编写，Quartus7.1综合，ModelSim6.2g se仿真，应用了opencores.org上的开源FFT IP核，加入了8051总线接口和ram
lab2_Freq_20120510
- 用verilog写的频率计，上课的时候用的。Spartan - 3E开发板。-verilog
ImageRotate
- 利用verilog实现图像旋转。本程序是基于XILINX公司的ISE实现的。-Verilog image rotation. This procedure is based on XILINX' s ISE.
DIV
- 奇偶分频，输入方波信号与分频系数，则输出分频后方波-Parity divider input square wave signal with the frequency division factor, output frequency division behind the wave
ch375_sof
- 南京沁恒电子生产的USB通讯芯片CH376的相关FPGA程序，基于NIOS核的C程序。-Nanjing Qin Heng electronic production procedures related to FPGA USB communications chip CH376-based NIOS core C program.
SDI_PassThr_SZ
- Xilinx SDI参考设计，Verilog/VHDL源代码和相关文档等-Xilinx SDI pass through Verilog/VHDL source code