资源列表
traffic
- 交通信号灯实验，南昌大学EDA课程，绝对有用-Experimental traffic lights, Nanchang University EDA course, absolutely useful
ZHWX
- DDS 产生正弦信号，OOK，AM三种波形。 使用xilinx FPGA VHDL-DDS. Resulting in sinusoidal signal, OOK, AM three waveforms. Using xilinx FPGA VHDL.
Quartus_II_15.0_crack_Windows
- Quartus_II_15.0破解器_Windows版-Quartus II 15.0 crack for Windows
rs232-485-422
- 该文件含有串口收发编解码模块和自动识别波特率模块-This file contains the serial transceiver module and the codec module Automatic baud rate
pcie_ctrl_module
- pcie genx4 控制器模块 verilog，直接读取内存和写入内存-pcie gen4 controller module verilog, direct memory read and write memory
gtx_drp
- 高速串行设计FPGA-GTX IP设置生成drp模块，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接-High-speed serial design FPGA-GTX IP setting generation drp module, dynamically configurable rate 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link
gtx_interface_ip
- 高速串行设计FPGA-GTX IP设置生成，可动态配置速率2.4Gbps，1.2Gbps，0.6Gbps，自适应链接-High-speed serial design FPGA-GTX IP settings generated dynamically configurable rate of 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link
colorchecker
- coloecheck VGA格式标准色卡生成，可支持任意分辨率设置 verilog-colorchecker VGA format standard color card production, can support any resolution settings
crc16_d8
- 此代码采用Verilog语言实现8位CRC校验功能，采用CRC-ITU标准制定的CRC16校验-This code USES the Verilog language function of eight CRC check the CRC- ITU CRC16 calibration standards
7-segment-counter
- 7 segment counter in VHdl-7 segment counter in VHdl
TECOM
- fpga永磁同步电机转矩的控制算法，很实用-fpga pmsm te
sos_module
- 用FPGA实现sos摩尔密码，即输出电平信号短长短。就是有次序的控制输出莫斯密码的“点”，“画”和“间隔”。而 control_module.v 是一个简单的定时触发器，每一段时间都会使能sos_module.v。-Realized by FPGA sos mole password, the output signal level of short duration. There is a sequence of output control points Moss password,