- cktxc-BIOS 利用BIOS功能调用实现两台微机间串行通信的C语言程序
- jabba is a basic Jabber client written in C++ using ncurses. It was one of my early university projects so it s value is mostly educational but it works :)
- matlab 采用动量梯度下降算法训练 BP 网络训练样本定义如下： 输入矢量为 p =[
- Bidirectional-search 最小统计噪声估计的双向搜索代码
- XP_linphone windows XP下编译linphone详细步骤
- BPSK 基于QPSK的调制解调系统
资源列表
VGA_pic_200x200x3(ok)
- altera 系列FPGA实现的VGA显示8色的图片，调试通过，开发环境quartusii , 语言verilog。-Altera series FPGA to achieve the VGA display 8 color images, debugging through, the development environment QuartusII, language verilog.
fft1024
- 1024点fft FPGA硬件实现 能在altera ep4sgx230kf40c2 完全实现-1024 point fft FPGA hardware implementation
spartan_mig20
- programer for FPGA with spatan
practica1
- tester.vhd library IEEE use IEEE.STD_LOGIC_1164.all use IEEE.STD_LOGIC_ARITH.all use IEEE.STD_LOGIC_UNSIGNED.all LIBRARY lpm USE lpm.lpm_components.ALL entity practica1 is port ( RESET : in std_logic clk :
uart_rx
- 串口接收模块代码，根据设定的串口波特率，可以正确接收串口的数据-Serial receive module code, according to the set baud rate, serial data can be correctly received
timer16
- 十六进制计数器的的Verilog实现。内有整个工程，包括tb文件。仿真可通过-realizaiton of timer16
seller_moore
- 用Verilog实现十六进制计数器。内含有整个完整工程。包括tb文件。-realiaztion of timer16 using verilog
mux31
- 三选一选择器的Verilog实现。三个输入端，一个片选端。-realization of mux31 using verilog.
mux21
- 二选一选择器的Verilog的实现。二输入，一片选段。-realization of mux21
piccolo
- piccolo 密码算法的Verilog实现-piccolo algorithm
XuLie
- 序列检测机，可检测8位数字序列，米勒型状态机-Sequence detector can detect 8-digit sequence, Miller-type state machine
cpld
- 使用cpld完成多个串口切换通信，能够完成快速通信，已经完成验证-Using CPLD to complete multiple serial communication