资源列表
FSMpart5
- FSM Verilog implementation of the final part of lab 7 of altera s verilog tutorial for de2115 fpga.
FSMpart4
- Verilog FSM implemetation for altera s lab 7(part IV) for de2115 fpga.
part3FSM
- Verilog FSM implementation for altera s lab(part 3 of lab 7).
FSMpart2
- Verilog implementarion of FSM. Solution for altera s lab 7 part2.
gpio-master
- 基于WISHBONE总线接口的GPIO模块verilog代码实现，包含详细GPIO定义文档，testbench，RTL仿真与综合环境-WISHBONE interface to GPIO verilog code, GPIO define, RTL sim, syn
UART-master
- UART通讯接口verilog代码实现，uart_tx子模块和uart_rx子模块，包含详细testbench-UART interface verilog code, uart_tx、uart_rx， testbench
lcd
- 采用Xilinx公司的Virtex-5芯片实现lcd程序-Using Xilinx' s Virtex-5 chip lcd procedure
apbi2c_latest.tar
- APB总线协议转I2C总线协议的接口IP，verilog代码实现，包含详细testbench-APB bus interface to I2C bus interface IP，verilog code
apbtoaes128_latest.tar
- AES加密算法verilog代码实现，基于APB总线接口数字IP，包含详细的testbench-AES encryption algorithm verilog code, based on the APB bus interface digital IP, contains a detailed testbench
DES-Verilog-master
- DES加密算法硬件verilog实现，包含testbench，加密主模块encrypt，明文变换模块LRToCiphertextConverter，NextRi模块等子模块。-DES encrypt verilog
PCIe
- 使用Altera PCIe IP核,补充PCIe事物层，完成了PCIe设备端硬件设计。Windows和Linux下，安装合适驱动后，可读写PCIe设备。-Use Altera PCIe IP core, supplement PCIe transaction layer, complete PCIe device side hardware design
DDS(ok)
- 制作ROM正弦表并填充FPGA内部ROM，通过调用内部数据实现正弦波输出，开发环境quartusii , 语言verilog , 调试通过 ， 附有modelsim调试结果。-Make ROM sine table and fill the ROM internal FPGA, by calling the internal data to achieve the sine wave output, development environment QuartusII, Language Veri