资源列表
tswc_state
- XILINX SPORTAN3 实现状态机功能，状态切换，可以改变状态切换的时间。 -XILINX SPORTAN3 implement state machine function, state switch, the switching time may be changed.
studyFFTcore
- 调用FPGA的IP核实现FFT运算，在xilinx的vertex4sx55FPGA的实现-Call FPGA implementation of the IP core FFT computation, in the Xilinx implementation of the vertex4sx55FPGA
mcode_FPGA
- 伪随机码发生器，次源码已经经过了测试并通过时序仿真验证没有任何问题，此小m序列发生器的特征多项式我没有写，但我建议大家在看原代码之前还是先看下扩频通信中m、M、Gold序列的原理，只有这样才能够真正的明白伪随机码发生器发生器的原理。-mcode_FPGA
ZCYL
- 组成原理课设，设计一个计算N的平方和的微型机，N小于等于8-Composition principle lesson set, design a calculation of the square of N and the microcomputer, N less than or equal 8
VHDL-example
- 利用VHDL语言编写的多个参考程序，适用于各种环境，编程时使用的是altera的开发板-Verilog language reference procedures applicable to a variety of environments, programming altera development board
DDS
- 这个是在quartusii和matlab simulink下搭的dds的模型，已经经过仿真是可以的。并且已经转为vhdl代码。-This is quartusii and matlab simulink model to catch the dds, has been the simulation is possible. And has to vhdl code.
AI_WP_173
- nice motor contorl atrical
shift_reg
- 移位寄存器，Verilog实现，有实验说明文档。-Shift register, Verilog implementation, there is experimental documentation.
IP-code(8051-cpu-jtag-vga_lcd-i2c)
- ip核源码，包含8051,cpu,jtag,vga_lcd,i2c，使用vhdl语言编写，-ip nuclear source, including 8051, cpu, jtag, vga_lcd, i2c, using vhdl language,
Simple-calculator
- Simple calculator using VHDL coding
systemverilog+assertions应用指南
- system verilog assertion介绍(system verilog assertion introduction)
AD9833
- VHDL语言 状态机实现AD9833信号的产生-VHDL language state machine to achieve AD9833 signal generation