资源列表
mem_test
- 简单的存储器内核测试，已经验证通过，VLOGER编写-Simple memory core testing, has been adopted to verify, VLOGER prepared
firfilter
- 实现一个FIR滤波器，基于直接型型算法 输入数据宽度：8位 输出数据宽度：16位 阶数：16阶 滤波器经转换后（右移16位）的特征参数为： h[0]=h[15]=0000 h[1]=h[14]=0065 h[2]=h[13]=018F h[3]=h[12]=035A h[4]=h[11]=0579 h[5]=h[10]=078E h[6]=h[9]=0935 h[7]=h[8]=0A1F
S8_test
- 本程序用来测试开发板上所有的设备。 1、VGA输出8位色彩的条纹； 2、PS/2键盘输入字符可以传输到LCD和串口调试终端上； 4、拨码与按键开关与4位LED相连-This procedure is used to test all the equipment development board. 1, VGA output 8-bit color stripes 2, PS/2 keyboard input characters can be transmitted to the
Introduction-_FPGA
- fpga的初级教程，分为一和二，请认真学习-fpga primary curriculum is divided into one and two, please carefully study
keshe
- 计算机组成原理课设，做了一个cpu，希望对同学对计算机组成原理的学习有帮助-Computer organization course designed to do a cpu, the students hope to learn on the computer organization help
photo-frame
- 一篇用FPGA做数字相框的论文.有实际制作指南.-a paper on Digital photo frame with a FPGA.
filter_2d
- XILINX ISE FILE FOR FPGA IMPLIMENTATION OF 2D FIR FILTER USING MODIDIED BOOTH ALGORITHM
fault
- fault minimization using genetic algorithm
8253
- 8253可编程定时器/计数器芯片 VeriLog实现-8253 programmable timer/counter chip VeriLog achieve
VGA_test3
- 利用FPGA实现VGA的驱动，驱动VGA进行工作并通过该功能在显示器上显示一定的内容(my english is poor, so have a look at the chinese)
adder8
- 基于vhdl的八位加法器，以两个四位加法器为基础(Eight bit adder of VHDL)
Constraint-Based-Verification
- 系統化驗証方法及實例探討Assertion, Constraint synthesis-Electronic Design complexity getting higher, the verification work needs to be fully understood