资源列表
traffic_control
- 设计制作一个用于十字路口的交通灯控制器 有一组绿、黄、红灯用于指挥交通，绿灯、黄灯和红灯的持续时间分别为20秒、5秒和25秒； 当有特殊情况（如消防车、救护车等）时，两个方向均为红灯亮，计时停止，当特殊情况结束后，控制器恢复原状态，继续正常运行-design a crossroads for the traffic signal controller is a group in green, yellow and red lights to direct traffic. green,
adc0804_new.rar
- AD0804驱动，使用新的查表方式，可大大的降低数值运算，节省CPLD的资源,AD0804 driver，using a new method_look up table,which can save a lot of resources of CPLD
MAC_4_CSA
- MAC-4bit verilog source code with CSA style
VHDL4
- 一个使用VHDL的AD转换程序，让你明白AD在VHDL中如何编程。-One of the AD conversion process using VHDL, so that you understand how the AD in the VHDL program.
VerilogHDL解码DS18B20
- DS18B20解码代码，verilogHDL实现。
i2c
- 用I2C程序模拟TTL液晶显示的主模式的工作过程-Process simulation with I2C master mode TTL LCD display the working process
firfilterr
- this is a coding file for FIR filter in vhdl
firfilter
- this is a coding file for FIR filter.
divider13
- 这是一个13分频器，可以进输进来的信号进行13分频后输出-This is a 13 frequency divider which can transfer the input clock signal into a 1/13 clock signal.
vga_controller
- 24bit的LCD控制器，由Verilog编写，带有Avalon总线接口，可以在SOPC中直接调用-24bit' s LCD controller, prepared by the Verilog with Avalon bus interface, you can directly call the SOPC
verilog_Digital-tube-scanning
- 仿顺序思想编写的数码管扫描，分为顶层模块、数据产生模块、数据传输模块、数码管扫描模块，直白易懂。-Written imitation of the order of thinking digital scanning, divided into top-level module, the data generation module, the data transfer mode Block, digital scanning module, straightforward and easy
hierarchical-code
- Abstract—This paper presents a highly effective compactor architecture for processing test responses with a high percentage of x-values. The key component is a hierarchical configurable masking register, which allows the compactor to dynamically ad