资源列表
psk
- 应用verilog语言编写实现二元相移键控调制过程-Application verilog language to achieve binary phase shift keying modulation
ISA
- ISA总线接口，采用verilog HDL语言编写，值得参考！-ISA bus interface, using verilog HDL language, worthy of reference.
traffic_led(verilog)
- 交通灯verilog源码，在实验板上测试通过-Verilog source of traffic lights, the board tested in experiment
DC-motor-controller-and-its-control
- 基于VHDL语言的直流电机控制器及其控制，本控制系统的总体结构,下位机是整个高频疲劳试验机控制器的核心。用于实现产生控制试验机的控制信号和数据，反馈信号的处理，以及和上位机进行数据通信。其控制功能强弱也直接影响着整个控制器性能的好坏-DC Motor Based on VHDL controller and its control, the overall structure of the control system, the next bit machine is the high-freq
keyboard_control
- 用VHDL语言实现键盘控制，用于fpga实现键盘输入的应用-keyboard control vhdl program
communication_232
- FPGA 串口程序 VERILOG-FPGA serial procedures
led_vhdl
- LCD点阵阵控制,可输出不同的图形和位置.可随意调整显示格式.
usb20arm_by
- vhdl for usb2.0 interface-vhdl for usb2.0
DS18b20
- DS18B20测温程序,DS18B20软件模拟-DS18B20 measurement procedures
pfl_d
- fpga的pll锁相设计，altera器件EP1s25的选用、设计-phase-locked pll of fpga design, altera devices EP1s25 selection, design
camera_len_con
- 一个摄像机镜头远程控制C程序，采用PELCO-D和PELCO-P自动识别协议，通信速率：1200/2400/4800/9600四种，镜头反持类型：直流和止进两种，通过P1.0选择，当前使用的CPU型号为STC12C5201系列-A camera lens remote control C program, using PELCO-D and PELCO-P automatic recognition agreement, the lens counter-holding types: DC an
ReactionTimer
- Reaction Timer verilog code, can be downloaded on texas NEXYS2 or NEXYS3 board to test the reaction time by pressing the buttons.