资源列表
2to10
- 2 to 10 bcd under vhdl langage in maxplus2 good one
MemManager
- memory manager vhdl code
conunt
- eda电子钟计时模块的实现 eda电子钟计时模块的实现 eda电子钟计时模块的实现-eda count eda count eda count eda count eda count eda count eda count eda count
FIFO-queue-using-a-DPRAM
- FIFO queiue using DPRAM goog project
traffic_lights
- 运用Verilog HDL编程语言，实现十字路口的交通灯功能，可在FPGA等硬件上进行仿真（默认硬件晶振为50MHz）。-Using Verilog HDL programming language, to achieve the crossroads of traffic lights function, can be simulated in FPGA hardware on (the default hardware crystal is 50MHz).
lcd12864_5
- 可以在lcd12864上进行显示字和显示图像的立即转换。-Lcd12864 can be displayed on the display images of words and the immediate conversion.
MAC
- 在FPGA硬件上，使用verilog语言编写的一个乘累加器程序。-FPGA hardware, a multiply accumulator verilog language program.
ad7938
- AD7938控制程序，用VERILOG HDL语言编写，已在平台测试。-AD7938 control procedures, the use of VERILOG HDL language, and has set up a file in the platform test.
trafficlight
- VHDL实现红绿灯，multisim测试通过，可直接烧录到FPGA板上进行测试,带testbench-VHDL realize traffic lights, multisim tested, can be burned directly to the FPGA board for testing, with testbench
frecount
- 基于vhdl的频率计控制器模块设计，已经经过调试，可直接调用-Vhdl based on the frequency of the controller module design, debugging has been directly call
FIFOadnVHDL
- FIFO （先进先出队列）是一种在电子系统得到广泛应用的器件，通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。
D-type-flip-flop
- 设计一个D型触发器，输入CK（时钟信号, ↑表示上升沿时刻），D（数据），Clear端（“0”时清零），输出Q-Design of a D-type flip-flop, the input CK (clock signal, ↑ indicates rising time), D (data), Clear end (" 0" is cleared), the output Q