资源列表
serial
- 用VHDL实现串口与电脑通信，已调试过，没错误-it can be used to commuciate serial with computer
AM2901
- 计算机系统设计课程实验，AM2901的vhd代码-Computer systems design course experiment, AM2901 vhd code
AD9512_VHDL
- FPGA通过SPI总线控制Analog公司的射频时钟分配芯片的程序，在需要用到高速时钟（GHz）的电路中经常采用，比如数据采集卡及信号回放卡中会经常用到该功能，已经在产品中得到验证，工作稳定。-The VHDL code of controlling AD9512 of Analog Device
asy_FIFO
- 用Verilog实现FIFO的异步设计，里面有详细的代码和各个模块的代码，经过调试可以使用-asynchronous FIFO design
sync_neg
- 本模块是利用时钟同步输入的异步信号，使信号用于状态机处理，减少跑飞的概率。-This module is to use asynchronous clock synchronization input signal, the signal for the state machine, decreases the probability of runaway."
Asynchronous-FIFO-design
- 异步FIFO是一种先进先出的电路，在异步电路中，由于时钟之间周期和相位完全独立，因而数据丢失概率不为零。如何设计一个高可靠性、高速异步的FIFO是一个难点，本代码介绍了一种解决方法。-Asynchronous FIFO is a kind of advanced first out circuit, in asynchronous circuit, as the clock cycle and phase between full independence, thus data loss pro
src
- 七位表决器 非常好的程序 欢迎免费下载-Seven voting very good welcome to download the program
source
- 实现永久流水灯的verilog .v文件-source verilog
lcd_driver_4bit
- it is a 4-bit lcd driver written in verilog .it will work on spartan 3 xilini devices.
alarm
- used to create simple alarm system
lcdctrl
- CFAH1602B-NGG-JTV LCD drive code -CFAH1602B-NGG-JTV LCD drive code
shizhong
- 下面是一个可在开发板上实现的时钟程序,不仅可以做为时钟用,还另外加了个跑秒的功能.-udp table for hotel management. In daily life have an important role, with verilog code