资源列表
8b10b编解码
- 8b10b编解码，aurora协议，遵照xilinx官网文档-8b10b encoder and decoder, aurora protocol
CLAAdd
- This zip folder contains the Carry look ahead in verilog HDL
VHDLDIV
- 文档里面的程序是用VHDL编程的分频程序，是将12MHZ的频率分频为1HZ和1KHZ，当然，也可以修改成任意频率的分频程序。(Document inside the program is programmed with VHDL frequency division program, is the frequency of 12MHZ frequency is 1HZ and 1KHZ, of course, can also be modified to any frequency frequ
code_gen_rtl
- GPS/GLONASS PRN code generator. VHDL sourse file
Verilog1
- 同步字检测程序，Verilog程序，初级编程-Sync word detection procedure, Verilog program, the primary programming
FPGA-URAT.rar
- FPGA与PC串口自动收发程序,verilog源程序,FPGA and the PC serial port automatically sending and receiving process, verilog source code
shop
- 自动售货机，支持5种商品的预设数量，价格，可以选择购买商品及其数量，可以输入0.5,1.5三种金额。支持找零。-Vending machines, supports five kinds of commodities preset quantity, price, and quantity of goods you can choose to buy, you can enter the amount of three 0.5,1.5. Support homing.
37724082FIFO
- 基于Verilog HDL的异步FIFO设计与实现
multiply_8_VHDL
- 由8 位加法器构成的以时序方式设计的8 位乘法器，采用逐项移位相加的方 法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件，运行可用。-an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and
VHDLcontrolCurentmotor
- VHDL设计直流电机的典型例子，适合教学或自学案例-VHDL design Motor typical example, for teaching or self-Case
MCDESIGN
- VHDL详尽世界观 用于成品率的的语言,请大家 参考使用,并提出宝贵建议-VHDL detailed outlook for the yield of the language, please refer to the use, and put forward valuable suggestions
pipeline_streamlined_divider
- pipeline_streamlined_divider, 一个流水线的除法器，使用Verilog HDL语言编写-pipeline_streamlined_divider， a divider using pipeline technology in verilog HDL language