资源列表
chuanb
- 在qpsk调制模块中，需将码元转换成两位并行的码元输出，它有四种存在形式，正好对应qpsk的四相载波，实现qpsk调制。-Qpsk modulation module code converted into two parallel bit output, which has four in a form exactly corresponds to the qpsk The four-phase carrier to achieve qpsk modulation.
Axi4
- Dynamic routing is desirable because of its substantial improvement in communication bandwidth and intelligent adaptation to faulty links and congested traffic. However, implementation of adaptive routing in a network-on-chip system is not tr
main
- 红外解码LCD1602液晶显示 可显示已经解码成功的红外编码-IR decoding LCD1602 liquid crystal display can display the already successful infrared coding decoding
Verilog
- 32位存储器Verilog附带test文件，可以在modulesim仿真 还有加法、减法器，译码器等常用Verilog器件，都附带仿真test。-Memory test with Verilog
jop_core_bcfetch
- JOP内核字节码获取，很难找的东东，呕血之作-JOP core byte code access, it is difficult to find the price. Zhi for hematemesis
ENCODE
- 本源码实现交织编码，源码为VHDL语言。运行于发射端FPGA。-Interleaved Coded achieve this source, source code for VHDL language. Running on the transmitter FPGA.
m
- 由20位移位寄存器线性反馈产生的m序列的vhdl代码-20-bit shift register linear feedback sequence generated vhdl code m
fifo_uart
- 使用fifo完成的串口通信。verilog语言。-fifo-uart verilog
Temperature
- FPGA 用Verilog语言时序实现与DS18B20温度传感器读写，并把温度通过LCD来显示-FPGA with Verilog language implementation and timing DS18B20 temperature sensors to read and write, and the temperature displayed by LCD
phase-locked-loop-implementation
- 在FM0数据解码时，利用锁相环生成数据同步时钟信号。文件为锁相环实现。Verilog HDL-When FM0 decoding data using the phase-locked loop generates the data synchronizing clock signal. File for phase-locked loop implementation.Verilog HDL
bzfadmultiplier
- BZFAD MUltiplier Code In Verilog Possible Bugs
Pulse_tx
- 4路PPM 编码器，输入4位数字信号，输出ppm 脉冲序列，已测试过。-4bits ppm encoder.