资源列表
Lattice-DDR3
- littice ddr3的仿真教程，主要讲解怎么仿真littce 的ddr3，和littice ddr3的基本知识的讲解-explain the basics of lattice ddr3 simulation tutorial, mainly on how simulation little of ddr3, and littice ddr3 of
pld-tutorial
- pld的实践教程，完整详细的讲解适用于初学者以及研究开发人员-pld hands-on tutorials, full and detailed explanation for beginners as well as research and development staff
traffic
- vhdl实现交通灯的控制，具有行人优先原则，最大程度的实时监控-vhdl achieve control of traffic lights, with pedestrian priority principle, the greatest degree of real-time monitoring
14.3
- xilinx app1026 关于Ethernet的使用例程
2_Qsys_Intro_Lab
- altera 最新max10器件 qsys led demo，关键点在于它的运行是依靠tcl来执行-max10 led demo，using tcl to run
RS485
- FPGA/CPLD实现RS485通信协议，在Quartus ii平台上进行Verilog编程仿真-FPGA/CPLD realize RS485 communication protocol used to Verilog simulation on Quartus ii programming platform
FPGA-program-flow-chart
- altera fpga烧写流程，原创，详实。-altera fpga
URAT-VHDL
- vhdl版本的uart收发程序，方便实用-uart vhdl rx/tx
PSK-mod-demod-VHDL
- vhdl版本的bpsk调制和解调程序，超级实用-bpsk vhdl mod/demod
pseudo-random-number-VHDL
- 伪随机序列发生器的vhdl软件，有m序列和gold序列的算法-pseudo random number generator
113813_CONTADOR_TIEMPO_REAL_1
- vhdl xillin timer source code of an timer based on a Spartan 3E
texample1
- 32-bit shifter, 32-bit.Very goog as a study file.-32-bit shifter, shifter, 32-bit.Very goog as a study file.