资源列表
FIFO
- VHDL code for first in first out register
Desktop
- VHDL code for 16 byte ROM & n bit comparator & a full adder
mux_reg
- VHDL code for a multiplexer and a parallel/serial in parallel/serial out shift register
stoplight
- VHDL code for a 4 state stop light with police control input
BCD_adder
- VHDL code for a one bit comparator and an n bit register and a BCD adder
tristate
- VHDL code for a full adder and n bit full adder a tri state buffer and a flip flop
ahbmst
- amba总线的主设备用于实现基于amba总线的功能，这个事主设备的代码-amba bus for the main equipment amba bus based on the function of the code of the victim equipment
amba
- 这个一个基于amba总线的的vhdl语言程序描述，学习fpga总线开发的请看-The amba bus based on the procedures described in languages vhdl, fpga bus developed the study see
leon3
- 这个一个基于amba总线的leon3处理器的vhdl语言程序描述，学习fpga总线开发的请看-The amba bus-based processor vhdl language leon3 procedures described in the study developed fpga see bus
svgactrl
- 这是一个基于amba总线的svga lcd控制器的源码，请学习-This is a amba bus-based controller svga lcd source, please study
VHDL-1
- 数字电路设计,好东西-数字电路设计,好东西-------------------
593352pll
- 使用VHDL编写的数字PLL，对于想在FPGAzhong灵活使用时钟 的人有帮助。-Prepared by the use of VHDL digital PLL, the FPGAzhong would like flexibility in the use of the clock to help the people.