资源列表
Code-Structure
- decoder_using_with vhdl
book
- Verilog HDL与VHDL都是数字系统设计的硬件描述语言，VerilogHDL适合算法级，rtl，逻辑级，门级，而VHDL适合特大型的系统级设计。针对这些特点这两本书深入浅出的介绍了这两种语言。-Verilog HDL and VHDL design of digital systems is the hardware descr iption language, VerilogHDL suitable algorithm level, rtl, logic level, gate-lev
NIOS_JTAG_UART
- FPGA开发板上的JTAG——UART完成的工程设计，包括CPU内核设计合软件设计-FPGA development board JTAG- UART completed the engineering design, including the CPU core design combined software design
VHDL_wendukongzhi
- 基本空调温度控制-Temperature control
__FPGA_Prototyping_by_VHDL_Examples
- 在赛灵斯上用VHDL实现，串口，PS MOUSE, PS KEYBOARD..... 协议-on Xilinx,to achieve using VHDL too fullfill UART, PS MOUSE, PS KEYBOARD ..... prototype
NIOS_seddisplay
- NIOS七段数码管显示系统设计，包括完整的硬件合软件设计-NIOS Seven-Segment LED Display System Design
213123
- VHDL 经典参考书很不错 适合初学者 自己搜索-VHDL classic reference book is pretty good for beginners
LCD1602Display
- FPGA中LCD1602驱动开发设计，软件quartusII6.0，verilog-LCD1602 driver in the development of FPGA design, software quartusII6.0, verilog
454545445
- 很不错的资料 示意初学者 CHDL 很不错-Data indicate a very good very good beginners CHDL
SmartSOPC_Component
- smartSOPC NIOS IP core，周立功FPGA实验箱IP核-smartSOPC NIOS IP core, Zhou Ligong FPGA experimental box IP core
107215805CPLD_FPGA
- VHDL 很不错的电子书 适合初学者 和提高着-VHDL is very good river for beginners e-book bundle
FPGA_work
- 实际上使用VerilogHDL语言写的，开发环境为Quartus7.2，很不错的，基于de2的-VerilogHDL the language actually used to write, and development environment for Quartus7.2, very good, based on the de2