资源列表
fnd-clk
- FND, SEGment verilog code
Read_SPI_ADC
- This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 ADC and generates SPI_CLK and SPI_nCS of it and reads 12-bit serial data ADC and returns 12-bit parallel data.-This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 AD
altera-TimeQuest_User_Guide
- alter时序约束的开发者手册，从官方直接拿到的。-altera timing handbook，directly got xilinx.
xilinx-tcl
- Xilinx脚本约束手册，从官方直接拿到的，对Xilinx FPGA开发很有用的。-Xilinx tcl handbook, directly got Xilinx。
ps2
- ps2键盘扫描程序verilog实现，将按键值转化为扫描值-ps2 keyboard scanner verilog realization, the key will be converted to scan values
LED
- LED等循环点亮，verilog实现功能-LED lights light cycle, verilog to achieve functional
i2c_master_top
- I2C控制总线的顶层描述verilog代码，选项中没有verilog语言，故选择VHDL-The function descr iption of I2C bus top level
i2c_master_bit_ctrl
- I2C控制总线主机，按照字节写设计的verilog代码，由于选项中没有verilog这项，因此选择VHDL-I2C control bus master, according to the byte write verilog code design, because the option is not verilog this, so choose VHDL
i2c_master_byte_ctrl
- I2C控制总线按照word写，用verilog实现的主机写功能-I2C control bus according to the word write and write functions implemented by host verilog
i2c_slave_model
- I2C控制总线的重机模型，用于验证I2C设计是否实现了功能描述-I2C bus control heavy machine model, used to verify whether the design implements I2C Functional Descr iption
tst_bench_top
- I2C控制总线的测试平台testbench，用于验证I2C主机冲击交互的正确性-I2C control bus test platform testbench, used to verify the correctness of the interaction I2C master impact
pwm
- 一个宽度脉冲调制pwm的模板，因为是学习使用的，增加了数据输入以便在开发板的led灯中观看实验现象，输入数据越大led的亮度越大-A pulse width modulation pwm template, because it is learning to use, increasing the data input for viewing experimental phenomena in the development board led lamp, the greater the gre