资源列表
I2Creadorwrite
- 基于MAX II 系列 epm1270t iic的读写-Based on the MAX II family literacy epm1270t iic
siga
- 2014电子设计大赛e题固件模块代码，很好的实现功能。-2014 electronic design contest e Title firmware module code, very good to achieve function.
New-Compressed-(zipped)-Folder-(4)
- verilog code for sequence detection implemented on FPGA using quartus simulator
New-Compressed-(zipped)-Folder-(5)
- traffic light controller verilog code modelsim tested
meexternalletterforcsvtu
- ! E:\jogeshwer.zip: Cannot open E:\jogeshwer\RR4_mult_paper.docx The process cannot access the file because it is being used by another process. -! E:\jogeshwer.zip: Cannot open E:\jogeshwer\RR4_mult_paper.docx The process cannot access
Dchufaqi
- VHDL实现D触发器包括上升沿触发，下降沿触发，时钟触发-VHDL realize D flip-flop including rising along the trigger, falling edge trigger, triggered the clock
Lab2
- Flip-flops with enable
LCD
- 基于FPGA和Nios II的12864LCD驱动代码-Based on FPGA and Nios II of 12864LCD driver code
liushuideng
- 使用ise写的并行流水灯，体验顺序执行和并行的概念，容易学习-Use ise write parallel water lights, concept experience sequential and parallel execution, and easy to learn
paral_to_serial
- 用verilog HDL编写的并行接口转串行接口的程序。-The programming of parallel interface to serial interface with HDL verilog.
fenpin
- 用verilog HDL编写的任意数分频，包括偶数分频和奇数分频等。-The any number of points, including even frequency and odd frequency, etc..using Verilog HDL
mux3x2
- 基于VHDL的3选2功能元件的Quartus II实现-Based on 2 out of 3 functional elements Quartus VHDL realization of II