资源列表
Demo_03_VGA
- 基于FPGA的的VGA程序，由于开发板的原因，只能显示9种颜色，，用户可以自由拓展-FPGA-based VGA-program, because of the development board, can only display 9 colors,, users can freely expand
txmit
- uart设计，发送模块，无校验位。先输出一个低电平的起始位，然后从低到高输出8个数据位，接着是可选的奇偶校验位（这里没有），最后是高电平的停止位。-uart design, transmit module, no parity. First output of the start bit of a low level, and low to high output 8 data bits, then the optional parity bit (there is no), the last
VerilogUart
- UART 串口通信模块，Verilog 实现。已在Microsemi Actel FPGA A3PE1500 硬件验证通过。-UART serial communication module, Verilog implementation. Verified by Microsemi Actel FPGA A3PE1500 hardware.
code
- high pass filter and low pass filter
1st-wrk
- multiplier code using verilog
2nd-wrk-(1)
- verilog code for shifting of multiplier
code
- verilog code for intrusion matching
polynominal-multiplier
- verilog code for polynominal multiplier
4bit-adder
- 4 FIT ADDER FULL EXAMPLE IN VHDL LANGUAGE
wiegand
- Wiegand encoder Recive card number Save card number Mach saved and recived card number Resolve access status
costas
- costas锁相环matlab仿真代码，对costas环的研究和硬件实现具有指导意义。-Costas Phase-Loop MATLAB Code.
VHDL-qiangdaqi
- VHDL语言实现的抢答器功能，源码和原理图都包含在文件内，可以直接在FPGA上运行。-The VHDL Responder function, source code and schematics are included in the file, you can run directly on the FPGA.