资源列表
buzzer_sos
- verilog语言编写的能有次序控制输出莫斯密码SOS的模块。-verilog language written in order to have control of the module output Moss SOS password.
PS2
- 基于verilog语言不编写的键盘的PS2接口解码程序。-Verilog language is not written on the PS2 keyboard interface to the decoding process.
VGA_module
- 基于verilog语言编写的VGA协议的程序，用以驱动VGA接口的显示屏-Based verilog language VGA protocol procedures to drive VGA display interface
AD_sample
- AD采集模块,设计模块采集AD5270的输出数据-AD Collection module Design module to collect the output data of AD5270
Display_7seg
- Basys 3 开发板入门实验，按键控制7段数码管显示试验。-Basys 3 development board entry test, key control of the 7 section of the digital tube display test.
Oscilloscope
- Basys 3 示波器工程源代码，可以参考。-Basys 3 oscilloscope source code, can refer to.
spi_flash_VHDL
- winbon 的芯片w25p16 驱动，使用VHDL语言，输入时钟为125M，只要稍微修改IDLE里面的跳转状态机就能跳转到各个读写，或是擦除状态。-the chip is winbon w25p16. vhdl language. the sysclk is 125m. it is easy to jump to write , read, or erase status by change idle status.
my_second_fpga
- 用Quartus ii13.0写的二进制加法器，使用了IP核RAM，以及LCD显示，打开就能直接使用。-Using Quartus ii13.0 write binary adder, using the IP core RAM, and LCD display, open can be used directly.
my_temp
- 使用Quartus ii 13.0 写的读取DS18B20的工程文件，将读到的结果显示在LCD上并存储到RAM中。-Using Quartus ii 13.0 reading project file written DS18B20 will read the results displayed on the LCD and stored in RAM.
viterbi-decoder-verilog
- viterbi verilog implemetation based matlab-viterbi verilog implemetation based matlab
practise
- FPGA实验板设计一个数字跑表。根据题目要求利用VHDL语言设计出一个系统，包括分频器，开关消抖，使能控制，计数器，锁存器，数据选择器及显示译码器。-FPGA experimental board design a digital stopwatch. According to subject the use of VHDL language to design a system, including the divider, switch debounce, enable control, c
OFDM_Convolution
- 自己写的卷积码，能实现仿真结果,有testbench文件-Write your own convolution code, simulation results can be achieved