资源列表
i2c_ms5611
- FPGA实现 I2C 总线读取MS5611气压计的程序-FPGA implementation of the I2C bus to read the MS5611 barometer
vip_ex9
- 本段源码实现功能为从摄像头采集到VGA输出的FPGA代码，内附编译好的工程文件-This segment functions as a collection source implementation the camera to the VGA output of the FPGA code, containing compiled project file
h264
- This is an example top level module for the H264 submodules. Each implementation will differ at the top level due to differing number of video streams, resolution, and RAM type and interface. This is thus just a skeleton implementation.- T
vga_lcd
- VGA LCD interface Uses gray codes to move one clock domain to the other. Flags are synchronous to the related clock domain - empty: synchronous to read_clock - full : synchronous to write_clock-VGA LCD interface Uses gray codes to
e1-framer
- e1 framer / de-framer based on itu-t standards state machine using GRAY CODE (or trying to use GRAY CODE
ddr_sdr
- DDR SDRAM Controller Core - has been designed for use in XILINX Virtex II FPGAs - works with DDR SDRAM Device MT46V16M16 without changes - may be easily adapted to any other DDR SDRAM device-DDR SDRAM Controller Core - has been designe
jpeg-coder
- EV_JPEG_ENC core is intended to encode raw bitmap images into JPEG compliant coded bit stream. JPEG baseline encoding method is used.
ex15
- vhd数码管测试源码，同时六个数码管控制，显示。-using ALTERA s FPGA design, QUARTUS software development platform.
CLOCK-CODE-VHDL
- VHDL源码程序，功能完整的时钟电路代码-using ALTERA s FPGA design, QUARTUS software development platform.VHDL CARD,
irdaGET
- 红外通讯接收，irda通讯接收，红外通讯测试-Infrared communications received, irda communications received infrared communication test
sed
- CPLD数码管程序,详细的7段式数码管程序。-CPLD verilog program
cal
- 针对CPLD实现简易计算器的程序。全部程序都在了。-cpld cal program