资源列表
fifo
- FIFO源码以及测试文件基于ISE14，Verilog语言编写，全部工程。-FIFO based on source code and test files ISE14, Verilog language, the whole works.
ML505
- ML505开发平台测试的工程(采用嵌入式系统实现)，整个工程。-ML505 development platform for test engineering (embedded systems implementation), the whole works.
sp605PCIe
- xilinx评估板sp605的PCIe的verilog源程序(已经经过调试)-Evaluation Kit for PCIe-sp605 xilinx verilog source (which has been commissioning)
Xilinxml505-
- 这个文件包含了在Xilinx公司的ml505 FPGA上的位码文件和配置文件，可以直接下载使用-This file contains the company s ml505 FPGA Xilinx bit code and configuration files, you can directly download
vhdl_100_ex
- VHDL语言100例详解，时候初学者学习使用-100example of vhdl
spi
- SPI通讯协议 应用VHDL语言编写实验SPI通讯-SPI VHDL
spi_ipcore
- 比较实用的SPI Verilog 编程，里面有仿真时序和源代码，简单改一改可直接，支持SPI双模式。-More practical SPI Verilog programming, which has simulation timing and source code, simple and can be directly altered, supports SPI dual mode.
SPI_Master
- 在FPGA中此源代码可作为SPI的主机传输代码，如有分开用的时候，此源代码会很方便，简单易懂-This source code in an FPGA can be used as SPI host transmission code, if separated by time, this source will be very convenient, easy to understand
64KAIGUAN
- 此代码是一分64路开关，通过串口控制具体开关的关断，简单，清晰-This code is a sub 64-way switch, via the serial control switch off specific, simple, clear
7duanshumaguan
- 7段数码管，显示计数器计数的个数，源代码简单，清晰-7-segment display counter counts the number of source code is simple, clear
uart-verilog
- 经典rs232串口Verilog源代码，晶振可随意根据具体情况更改，代码风格非常清晰，明了！-Classic rs232 serial Verilog source code, the crystal can be altered depending on the circumstances, the code style is very clear, clear!
flappybird
- 这是我练手时写的一个小游戏，是基于flappybird游戏原理制作的，用硬件完成其功能。主要用Verilog语言完成功能描述，通过ps2键盘的空格键控制飞翔，在VGA上进行显示。本工程已在basys2实验开发板上进行验证，画面略显粗糙，见谅。-This is what I wrote when practiced hand of a little game, is based on the principle of making flappybird game, with the hardwar