资源列表
code
- 把MII接口接收的4比特并行数据转换为8比特的并行数据输出。-convert 4 bit data to 8 bit data
code
- A、B两串行数据转换为并行数据，然后进入加法器模块，进行相加输出。-A, B two serial data is converted to parallel data, and then enter the adder module, add the output.
code
- 7位表决器，实现投票选择结果呈现； 减法器编码。-7 bit voting machine, realize the voting choice results present the encoding.
code
- 动态扫描键盘，然后把按键结果显示在LCD上，相关使用去抖功能-Dynamic scan keyboard, and then the key results are displayed on the LCD, the use of the shake function
code
- 经典电路设计（华为） 以及设计电路约束文件（华为）-Classical circuit design (HUAWEI) and the design of the circuit constraint file (HUAWEI)
ADS8509
- FPGA驱动高输入电压范围的ADS8509芯片，采样范围广，适合前端大信号处理-FPGA drive a high input voltage range ADS8509 chip, sampling a wide range, suitable for large front-end signal processing
DAC902_model
- 用verilog写的12位并口DAC902 模块。可在FPGA上运行-Written in verilog 12 parallel DAC902 module.Can be run on the FPGA
segled
- 数码管fpga Verilog HDL代码-Digital fpga Verilog HDL Code
sdram
- ISE14.4环境编程，XILINX spartan3E,SDRAM完整编程-xilinx sdram
sdram_5
- SDRAM的verilog描述，包含顶层设计，测试平台代码，精确描述-SDRAM is verilog descr iption, including top-level design, testbench code, an accurate descr iption of
nfc
- 近场通信的verilog描述，包含向量名定义，顶层设计等等的精确描述-Verilog descr iption of near field communication, including the vector name is defined, an accurate descr iption of the top-level design, etc.
ram_3
- RAM的verilog描述，包含向量名定义，顶层设计等等的精确描述-RAM in verilog descr iption, including vector name is defined, an accurate descr iption of the top-level design, etc.