资源列表
adder_shifter_counter
- 用VHDL写的全加器，移位寄存器，和计数器，并有文档说明，非常详细。-Using VHDL write full adder, shift registers, and counters, and is documented in great detail.
shuanglu_DDS
- 双路DDS，能实现两路同频不同相的各种波形，并附有和STM32的接口程序-Dual DDS, can achieve two different phases of the same frequency of various waveforms, along with and STM32 interface program
debun1
- 使用D型正反器,使開關防彈跳電路,規劃一個模組電路,也可組合多個模組,來配合多個開關輸入-D-type flip-flop, the switch anti-bounce circuit, planning a modular circuit can also be a combination of multiple modules to fit more than one switch input
Decoder2x4_A
- 基本的2對4解碼器,方便給4位多工7段LED的掃瞄控制-The basic two pairs 4 decoder, easy to work more than four 7-segment LED scanning control
Decoder3x8
- 把2x4解碼器再擴展為3x8解碼器,可控制8個LED掃描電路的驅動-The decoder then extended to 2x4 3x8 decoder can control eight LED driving scanning circuit
Decoder7447
- 基本的7段LED,解碼電路,也可更改相關的輸出控制碼,對應相關的顯示-Basic 7-segment LED, decoding circuit can also change the associated output control codes corresponding to the associated display
sw_bit8_latch
- 組合8個開關防彈跳,再加栓鎖電路,可讓開關動作更穩定-A combination of eight key anti-bounce, plus latch circuit allows the switching action is more stable
DDS_sinwave
- 基于FPGA对DDS芯片的仿真。能产生10M以上正弦波。并且波形不失真。-Simulation of DDS chip based on FPGA. Can produce more than 10M sine wave. And the waveform is not distorted.
FPGA_PWM
- 通过FPGA产生PWM波，实现频率与占空比均可调，移植方便快捷。-Produced by the FPGA PWM wave frequency and duty cycle can be adjusted to achieve convenient transplant.
mdio_slave_interface
- Management Data Input/Output Interfaces, or MDIO, are specified in the IEEE 802.3 standard. Their primary application is to provide a Serial Management Interface (SMI) to transfer management data between an Ethernet Media Access Controller (MAC)
hdb3
- 使用FPGA将伪随机码转换成DHB3吗，及解码HDB3码-encode and decode hdb3 using verilog HDL
sin_quartus9.0
- 用Verilog实现不同相位的正弦波波形输出，使用到ROM查表方式，对不同相位的地址进行合成后查表得到不同相位的正弦波。-Implementation of Sine wave output with different phase.