资源列表
hdl
- 用Actel公司的Fusion系列FPGA开发的LCD实验程序-Fusion with Actel s FPGA development series LCD Experimental procedures
RTC_Test_Top
- 用Actel公司的Fusion系列FPGA开发的RTC实验程序-With Actel' s Fusion Series FPGA development of experimental procedures RTC
DW8051_verilog
- DW8051单片机的设计，用HDL设计，详细的HDL设计-DW8051 microcontroller design, HDL design, detailed design of the HDL
cpu
- 用VHDL语言设计简单的CPU，重点设计微操作代码，然后设计CPU各组成模块，最后根据设计的微操作设计微指令，验证设计的正确性。可基本实现加、减、乘、除、移位、循环等操作。-VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the f
division
- 分别用分频比交错法及累加器分频法完成非整数分频器设计。-Points were staggered method and frequency than the frequency accumulator law to complete the design of non-integer divider.
myclock
- 用VHDL语言实现一个能显示时、分、秒的时钟：可分别进行时和分的手动校正；12小时、24小时计时制可选，12小时制时有上下午指示；当计时到预定时间（此时间可手动设置）时，扬声器发出闹铃信号，闹铃时间为10秒，可提前终止闹铃。-VHDL language used to achieve a display hours, minutes and seconds of the clock: when can be manually corrected and points 12 hours, opt
DE2_TV
- 基于DE2开发板，视频图像显示设计源代码，代码调试成功-based DE2 development board ,it is vhdl resourse code
PS2
- 使用FPGA读取键盘的例子，同时读取数据可以由数码管显示。-Read the keyboard to use the example of FPGA, at the same time data can be read by the digital display.
107215786i2c_master_verilog
- Verilog for I2C core source code
43680540SPI_Core
- Verilog for SPI Core source code
DPD_LUT
- 一种基于LUT的预失真方法。其中的一部分，有参考价值。-one method of DPD based on LUT
交通信号灯
- 电子设计自动化中关于交通信号的转换的实现程序，基于VHDL语言实现的-Electronic design automation in the conversion of traffic signals on the realization of the procedure, based on the realization of VHDL language